EK-K7-KC705-CES-G-J【PDF 3/62 页】KINTEX-7 FPGA KC705 EVAL KIT

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics

Table 2: Recommended Operating Conditions (1)(2) (Cont’d)

Symbol

Description

Min

Typ

Max

Units

GTX Transceiver

V MGTAVCC (11)

V MGTAVTT (11)

V MGTVCCAUX (11)

V MGTAVTTRCAL (11)

Analog supply voltage for the GTX transceiver QPLL frequency range

≤ 10.3125 GHz (12)(13)

Analog supply voltage for the GTX transceiver QPLL frequency range

> 10.3125 GHz

Analog supply voltage for the GTX transmitter and receiver termination

circuits

Auxiliary analog QPLL voltage supply for the transceivers

Analog supply voltage for the resistor calibration circuit of the GTX

transceiver column

0.97

1.02

1.17

1.75

1.17

1.0

1.05

1.2

1.80

1.2

1.08

1.08

1.23

1.85

1.23

V

V

V

V

V

XADC

V CCADC

V REFP

XADC supply relative to GNDADC

Externally supplied reference voltage

1.71

1.20

1.80

1.25

1.89

1.30

V

V

Temperature

Junction temperature operating range for commercial (C) temperature

0

–

85

°C

devices

T j

Junction temperature operating range for extended (E) temperature

devices

Junction temperature operating range for industrial (I) temperature devices

Junction temperature operating range for military (M) temperature devices

0

–40

–55

–

–

–

100

100

125

°C

°C

°C

Notes:

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

All voltages are relative to ground.

For the design of the power distribution system, consult the 7 Series FPGAs PCB Design and Pin Planning Guide ( UG483 ).

V CCINT and V CCBRAM should be connected to the same supply.

Configuration data is retained even if V CCO drops to 0V.

Includes V CCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%.

For more information, refer to the V CCAUX_IO section of 7 Series FPGAs SelectIO Resources User Guide ( UG471 ).

The lower absolute voltage specification always applies.

See Table 10 for TMDS_33 specifications.

A total of 200 mA per bank should not be exceeded.

V CCBATT is required only when using bitstream encryption. If battery is not used, connect V CCBATT to either ground or V CCAUX .

Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceivers User Guide ( UG476 ).

For data rates ≤ 10.3125 Gb/s, V MGTAVCC should be 1.0V ±3% for lower power consumption.

For lower power consumption, V MGTAVCC should be 1.0V ±3% over the entire CPLL frequency range.

Table 3: DC Characteristics Over Recommended Operating Conditions

Symbol

V DRINT

V DRI

I REF

I L

C IN (2)

I RPU

Description

Data retention V CCINT voltage (below which configuration data might be lost)

Data retention V CCAUX voltage (below which configuration data might be lost)

V REF leakage current per pin

Input or output leakage current per pin (sample-tested)

Die input capacitance at the pad

Pad pull-up (when selected) @ V IN = 0V, V CCO = 3.3V

Pad pull-up (when selected) @ V IN = 0V, V CCO = 2.5V

Pad pull-up (when selected) @ V IN = 0V, V CCO = 1.8V

Pad pull-up (when selected) @ V IN = 0V, V CCO = 1.5V

Pad pull-up (when selected) @ V IN = 0V, V CCO = 1.2V

Min

0.75

1.5

–

–

–

90

68

34

23

12

Typ (1)

–

–

–

–

–

–

–

–

–

–

Max

–

–

15

15

8

330

250

220

150

120

Units

V

V

μA

μA

pF

μA

μA

μA

μA

μA

DS182 (v2.8) March 4, 2014

Product Specification

3

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